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I am seeking an AMS Verification Engineer to join a global organisation based in Italy. You will have the chance to contribute to verifying the functionality and performance of Analog and Mixed-Signal designs. Key responsibilities will include, but are not limited to: • Developing verification plans for AMS designs. • Implementing and executing verification tests. • Collaborating with design engineers to identify and resolve design issues. • Performing functional and performance verification of analog and mixed-signal circuits. • Developing and maintaining verification infrastructure and automation scripts. • Analysing and debugging simulation failures. • Documenting verification procedures, results, and findings. • Participating in periodic reporting, design reviews, internal seminars, and training sessions. To be considered for this role, you must possess proven IC verification experience and a strong understanding of tools such as Cadence or Synopsys. For further information, please contact Parm Shergill.

***BRAND NEW ROLE, BRAND NEW TEAM, BRAND NEW COMPANY COMING TO PORTUGAL FOR THE FIRST TIME!!!*** Exciting opportunity for a Senior Digital IC Verification Engineer, to work in the beautiful setting of Portugal - in either Porto or Lisbon. Our client is one of the world’s fastest-growing Semiconductor companies, with HQ in the US and a 20-year background delivering high-performance solutions and ICs to a whole range of market areas including cloud computing, consumer, and automotive for some amazing companies & global brands! They are a billion dollar turnover company with enormous growth and development plans - so business is thriving for them! They are now seeking multiple Senior Digital IC Verification Engineers to help build a brand new team in their new design centre. Role: • UVM and System Verilog Verification. • Verification Metrics definition, Coverage analysis and debugging skills. • Knowledge and experience on setting up an ASIC Verification environment, methodology and flow. • vManager, vPlan and Regressions, etc. • Digital Test Plan definition / creating / set-up test benches • Knowledge of analog / mixed-signal (AMS) environments is a bonus • Knowledge of SOC verification is also a bonus Relocation assistance will be provided to join this friendly team, and you can expect a competitive salary package, great bonus scheme, exciting long-term career prospects with very good opportunities for promotion. For details, please contact Rob Hudson Visa sponsorship is also available if required.

Exciting opportunity to work on the latest cutting edge RISC-V technology in the semiconductor industry. In this new role as digital verification engineer you will have the opportunity to contribute to advanced technology nodes, consisting of RISC-V designs, ARM & CPU architecture, PCIe protocols and machine learning. I am looking to speak with digital verification engineers with 5+ years of experience - who have the following skills: Required: • Masters or PHD degree in Electronics / Microelectronics or similar field • 5+ years' experience in UVM environments & process • ASIC / FPGA development • System Verilog for IP / SOC Verification of digital ICs / ASIC IP or chips • complex ASIC designs & architecture for advanced technology nodes • Verification Metrics definition, Coverage analysis and debugging skills. • Knowledge and experience on setting up an ASIC Verification environment, methodology and flow. • vManager, vPlan and Regressions, etc. • Digital Test Plan definition / creating / set-up test benches • scripting / coding skills - C/C++, python etc. Bonus skills • RISC-V / CPU / GPU (this is a bonus, not required) • Knowledge of SOC verification is also a bonus ***Visa sponsorship can be offered if required (dependent on experience/qualifications)***

Senior Verification Engineer Based in the East Midlands, our successful and expanding Semiconductor client is seeking a Senior Verification Engineer. With a growing global reputation in High-Speed Communications, my client is expanding in the UK and are looking for a Senior Verification Engineer to play a vital role in the business, utilising the latest techniques, tools and technologies for design verification activities. Key requirements • 5+ years’ experience in the semiconductor industry. • Expert in digital design verification, using standardised methodologies, i.e. UVM • Experience in constrained random testbench development. • Proven track record in verifying complex designs (preferably in high volume ASIC applications) • Familiarity with high level protocols (e.g. PCIe, USB, DP) is an added bonus • Familiarity with SerDes is highly desirable • Experience with SystemVerilog Assertions (SVA) and formal verification is valuable On offer is a very competitive basic salary and bonus scheme, plus relocation and visa sponsorship if needed. For more information please contact Rachel Mason at IC Resources.