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Verification Engineer - Automotive IC Development - German Speaking Skills Required This is a brilliant opportunity for a German-speaking Verification Engineer to join one of Germany’s most successful fabless Semiconductor companies, based in Munich. As a Verification Engineer, you will be involved in developing the industry’s most advanced high-speed data transmission architectures for the automotive world. Key Skills: • Design and implementation of SystemVerilog UVM test benches • Regression simulations and evaluating simulation results • Develop verification plans • Knowledge of SystemC is a plus • Language skills in German If you would like to apply for this position, or find out more, please contact Lucy Edmondson.

ASIC Verification Engineer – Working on bleeding process nodes and at huge volume with Silicon Valley! Location: Oxfordshire (Hybrid Model) This is an interesting opportunity for an ASIC Verification Engineer to join a leading provider of high-performance client data centre and enterprise SSD products. As the ASIC Verification Engineer, you will get the opportunity to work on bleeding edge technology nodes (5nm) and with a billion dollar company with their own fab plant! To be successful you must live in a commutable distance of Oxford OR be willing to relocate from within the United Kingdom. I am looking for a proactive, delivery focused individual to contribute to time critical projects, an Engineer who likes to be technical challenged and solve problems. In this role, you will work closely with other ASIC team members, as well as with cross functional teams including architecture, firmware and validation. You will utilise and advance your ASIC verification skills while developing SSD controller ASICs targeting cutting edge silicon technology. Essential qualifications and skills: • Bachelor or Master’s degree in Electronic Engineering or related field. • PhD (desirable) • 12+ years of digital ASIC verification experience • Practical experience and understanding of:Requirement capture, verification planning and coverage closure • System Verilog and UVM test benches • Creation of UVM test benches • System Verilog assertions • Managing regression and debugging failures • Scripting languages (e.g. Perl/Python/TCL) As this is a Senior role, team leadership skills will be welcomed and there could be an opportunity to take on more of a ‘lead’ role. As an already hugely successful business you can expect; Private health insurance, Life assurance at 3 times your annual base salary, Permanent health insurance and Contributory Group Personal Pension Scheme. As this role welcomes Engineers with circa 12 years’ experience, the base will vary however you can expect a salary of between £80,000 - £95,000 depending on experience level. For more information on this opportunity, please contact Rachel Mason.

I am seeking an AMS Verification Engineer to join a global organisation based in Italy. You will have the chance to contribute to verifying the functionality and performance of Analog and Mixed-Signal designs. Key responsibilities will include, but are not limited to: • Developing verification plans for AMS designs. • Implementing and executing verification tests. • Collaborating with design engineers to identify and resolve design issues. • Performing functional and performance verification of analog and mixed-signal circuits. • Developing and maintaining verification infrastructure and automation scripts. • Analysing and debugging simulation failures. • Documenting verification procedures, results, and findings. • Participating in periodic reporting, design reviews, internal seminars, and training sessions. To be considered for this role, you must possess proven IC verification experience and a strong understanding of tools such as Cadence or Synopsys. For further information, please contact Parm Shergill.

We are seeking a CPU Verification Engineer to join one of the world’s leading RISC-V companies. This role can be based in Portland Oregon, or remotely. Our client was ranked among the top IP companies in the world. They are expanding exponentially, building their Verification teams in several international locations, and seek a CPU Verification Engineer to develop the next-generation RISC-V products for applications including 5G, AI and machine learning. The successful CPU Verification Engineer will have: • A BSc / MSc degree in Computer Engineering or similar • Proven experience in Hardware Verification, with expertise within SystemVerilog / UVM • A keen interest to work on RISC-V projects • Previous experience working on CPU / GPU Verification is ideal • A great work ethic, eagerness to learn • Eligibility to work in the US (visas cannot be sponsored at the moment) Our client offers competitive pay, promotes a very positive ‘work-life’ balance, and offers a great place to learn a variety of valuable skill sets within the industry. There is huge room for professional growth while they are expanding, through skill sets and promotions. Apply today! Contact Caroline Pye.

Verification Engineer - Senior and Principal levels Bristol, UK This is a fantastic opportunity to help support the build of a new Bristol based Chip Team, working on innovative, class leading silicon. My client has opened a small design centre in the bustling City of Bristol. They are developing a novel photonic-electronic architecture that will bring fully homomorphic encryption to the world. The development provides a huge opportunity to become the ubiquitous choice for this new upcoming market across multiple industry sectors. In order to achieve their goal of bringing this technology to the mass market, they are assembling a highly skilled team to build a complex SoC. With the successful recruitment of several Design and Verification Engineers into the team, they continue to build on this and are hiring for 2/3 more Verification Engineers. In this role, you would support the Verification group in defining the verification and validation strategy for the SoC. Working with the SoC Architect and Design team, you would help define and execute the strategy to build a SoC that achieves their technical and commercial goals. To be successful for this role you must have a strong background in SoC verification. UVM experience is a must. You will have: • A proven track record in SoC verification with exposure to all phases in the flow - requirements collection, methodology and test plans, testbench implementation, coverage closure, documentation etc. • Deep understanding of modern verification and validation techniques including formal, UVM/OVM/eRM, low power, emulation • Good knowledge of the SoC design flow from specification to silicon tape-out For more information and a chat about this superb opportunity, please contact Rachel Mason.

Design Verification Engineer - Berkshire This is an opportunity for a Design Verification Engineer to join an innovative environment and an organisation making changes in the technology sector. The Design Verification Engineer will join a team developing high-performance, low-power signal processing solutions in audio, voice, and haptics, delivering innovative end-user experiences and solving difficult challenges for new generations of mobile and consumer devices. You will join the team in Berkshire and will take ownership of all aspects of digital verification for complete IC developments, work on complex verification subsystems and will contribute towards improvements in methodology. Responsibilities • Definition of IC verification plan linking product requirements through to detailed testcases • Leading teams of verification engineers to deliver thoroughly verified ICs • Create reliable and reusable testbench for complex subsystems and ICs • Participate in verification Specialist Groups and contribute to the digital verification methodology discussions • Hands-on project design/verification involvement Required Skills and Qualifications • Metric driven verification - verification planning, requirements extraction - Directed and constrained random verification - Functional and code coverage analysis • SystemVerilog • Testbench design with verification frameworks like UVM/OVM, e, VMM • Debugging skills - RTL - Testbench, OOP - Gate level (including SDF) • Formal verification and verification qualification techniques • Scripting experience with Ruby, sh/csh, TCL, Make, Perl - advantage This is a hybrid on-site position and will follow a 2+ day in-office work schedule, with in-office days based on business needs and team preference. You must be based within commutable distance or be willing to relocate. On offer is a competitive base salary, bonus scheme and stock options. For more information please contact Rachel Mason at IC Resources

GPU UK Division - Senior and Principal Verification Engineers Work on cutting edge designs within a prestigious group! – Bristol, Cambridge, London outskirts, Manchester locations. I am seeking Senior and Principal level Verification Engineers to join my clients growing GPU Division. This position is a unique opportunity to exercise your hardware verification skills on cutting edge designs within the prestigious PowerVR Hardware Graphics group. Here you will exercise your skills on key components that meet latest demands and improvements for graphics, AI or connectivity processor and related IP. You will get the chance to work for a powerhouse whereby you will spend your time creating the graphics and AI chips that are at the core of your favourite electronic products, and they are expanding their IP portfolio to include RISC-V CPUs as part of their efforts to create the best Compute offering in the market! You will: • Be responsible for the delivery of all verification activities related to a GPU component or sub-system from early stages of verification planning to sign-off • Create verification plans, develop and maintain UVM testbench components • Participate in all stages of design specification definition providing feedback from the verification perspective • Develop testbenches in UVM, write tests, sequences, functional coverage, assertions & verification plans. • Be responsible for the definition, effort estimation and tracking of your own work • Be able to influence and advance our GPU verification methodology • Have the opportunity to lead, coach and mentor other members of the team • Participate in design and verification reviews and recommend improvements Qualifications • Have a proven track record of developing verification environments for complex RTL designs • Have excellent understanding of constrained-random verification methodology and challenges of verification closure • Be confident in defining verification requirements, and work out the implementation approach and details of a testbench • Be able to do root-cause analysis of complex issues and resolve them in a timely manner • Have excellent knowledge of SystemVerilog and UVM • Be able to develop new verification flows You might also have: • Experience leading teams • Graphics/GPU/CPU/SoC knowledge • Experience in wider verification technologies, such formal property-based verification and code mutation For more information and a confidential discussion on this superb opportunity contact Rachel Mason.

We are hiring for a Principal Verification Engineer to join our phenomenally successful Semiconductor IP client based in Krakow, Poland. Our client has achieved global success and is transforming the way SoCs (System-on-Chip) are designed and verified. They are expanding multiple design centres, including Krakow, and seek a Principal Verification Engineer to work as the technical lead for verification activities. The Principal Verification Engineer will lead advanced UVM testbench development and debug, drive and execute RTL verification test/coverage at system level and be central in refining the verification process and methodology across the business. Hybrid working is standard, with a few days in the office each week. Requirements for the Principal Verification Engineer position include: • A Master’s degree or PhD in Electronics Engineering or similar • An extensive background within digital IP / SoC verification • Expert skills in SystemVerilog / Verilog, and UVM • Excellent problem-solving and team working skills You can expect to enjoy working in a highly innovative, inspiring, friendly environment, that encourages productivity and creativity. Our client offers highly competitive packages and relocation assistance where needed. For details, please contact Caroline Pye.

Senior Verification Engineer Based in the East Midlands, our successful and expanding Semiconductor client is seeking a Senior Verification Engineer. With a growing global reputation in High-Speed Communications, my client is expanding in the UK and are looking for a Senior Verification Engineer to play a vital role in the business, utilising the latest techniques, tools and technologies for design verification activities. Key requirements • 5+ years’ experience in the semiconductor industry. • Expert in digital design verification, using standardised methodologies, i.e. UVM • Experience in constrained random testbench development. • Proven track record in verifying complex designs (preferably in high volume ASIC applications) • Familiarity with high level protocols (e.g. PCIe, USB, DP) is an added bonus • Familiarity with SerDes is highly desirable • Experience with SystemVerilog Assertions (SVA) and formal verification is valuable On offer is a very competitive basic salary and bonus scheme, plus relocation and visa sponsorship if needed. For more information please contact Rachel Mason at IC Resources.

Are you excited about R&D? An R&D Centre in Munich is looking for an experienced AMS Verification Engineer to work full time in their office (no hybrid working!). International candidates with strong skills in System C, System Verilog, Verilog A will be considered and visa can be provided for an exceptional candidate. A competitive salary package including a bonus will be offered. In your role you will have the following responsibilities: • System level model development for analog/mixed signal ASIC/IP according to both application and circuit design requirements • Implementation of user cases, fault injection and simulation test bench for analog system design verification • Maintenance and quality assurance for analog system models’ accuracy, scalability and reusability • Work with CAD group to improve the mixed signal verification methodology • Analog/ mixed signal fault modeling and simulation Requirements • Successfully completed Master or PhD. degree in Electrical Engineering, Microelectronics or any related fields of study and ideally experience in an R&D environment • Industry experience in analog/ mixed signal behavior modeling (e.g. System C, System verilog, Verilog A) • Knowledge or hands-on experience in analog/mixed circuit design (e.g. LDO, Buck, ADC, PLL) • Experience of analog/mixed signal design verification For more information and to apply, please contact Molly at IC Resources with your CV and a time for an initial call.

***BRAND NEW ROLE, BRAND NEW TEAM, BRAND NEW COMPANY COMING TO PORTUGAL FOR THE FIRST TIME!!!*** Exciting opportunity for a Senior Digital IC Verification Engineer, to work in the beautiful setting of Portugal - in either Porto or Lisbon. Our client is one of the world’s fastest-growing Semiconductor companies, with HQ in the US and a 20-year background delivering high-performance solutions and ICs to a whole range of market areas including cloud computing, consumer, and automotive for some amazing companies & global brands! They are a billion dollar turnover company with enormous growth and development plans - so business is thriving for them! They are now seeking multiple Senior Digital IC Verification Engineers to help build a brand new team in their new design centre. Role: • UVM and System Verilog Verification. • Verification Metrics definition, Coverage analysis and debugging skills. • Knowledge and experience on setting up an ASIC Verification environment, methodology and flow. • vManager, vPlan and Regressions, etc. • Digital Test Plan definition / creating / set-up test benches • Knowledge of analog / mixed-signal (AMS) environments is a bonus • Knowledge of SOC verification is also a bonus Relocation assistance will be provided to join this friendly team, and you can expect a competitive salary package, great bonus scheme, exciting long-term career prospects with very good opportunities for promotion. For details, please contact Rob Hudson Visa sponsorship is also available if required.

Exciting opportunity to work on the latest cutting edge RISC-V technology in the semiconductor industry. In this new role as digital verification engineer you will have the opportunity to contribute to advanced technology nodes, consisting of RISC-V designs, ARM & CPU architecture, PCIe protocols and machine learning. I am looking to speak with digital verification engineers with 5+ years of experience - who have the following skills: Required: • Masters or PHD degree in Electronics / Microelectronics or similar field • 5+ years' experience in UVM environments & process • ASIC / FPGA development • System Verilog for IP / SOC Verification of digital ICs / ASIC IP or chips • complex ASIC designs & architecture for advanced technology nodes • Verification Metrics definition, Coverage analysis and debugging skills. • Knowledge and experience on setting up an ASIC Verification environment, methodology and flow. • vManager, vPlan and Regressions, etc. • Digital Test Plan definition / creating / set-up test benches • scripting / coding skills - C/C++, python etc. Bonus skills • RISC-V / CPU / GPU (this is a bonus, not required) • Knowledge of SOC verification is also a bonus ***Visa sponsorship can be offered if required (dependent on experience/qualifications)***

ob Title: Principal Engineer - EPAD Product Verification Location: Barrow-In-Furness. We offer a range of hybrid and flexible working arrangements - please speak to your recruiter about the options for this particular role. Salary: from £45,628 depending on skills and experience What you'll be doing: Substantiating that the product is safe at various stages during procurement and build by execution of your Surveillance Plan and generation of objective evidence Ensuring build and design intent conformity through verification activities, at system and whole boat level Assisting in the conduct of design and safety classification configuration checks, as appropriate Supporting activities requiring input and support as part of configuration checks Analysis of root causes of failures Your skills and experiences: Essential: Degree qualified in Engineering (or working towards), or HNC with suitable experience Demonstrable and applied experience in Product Verification or Quality Assurance activities and build assurance Technical experience in Safety Assessments of design, evidence capture and risk analysis Desirable: Experience conducting technical investigations or audits Engineering Chartership or working towards Benefits: You'll receive benefits including a competitive pension scheme, enhanced annual leave allowance and a Company contributed Share Incentive Plan. You'll also have access to additional benefits such as flexible working, an employee assistance programme, Cycle2work and employee discounts - you may also be eligible for an annual incentive. The Product Verification team: As a Principal Engineer - Product Verification, you will primarily be responsible for ensuring product design intent and safety requirements are met across the submarine. You will also act as a subject matter expert (SME) for whole boat product verification, which will entail conducting assurance activities. This unique role will provide you with the opportunity to be involved with one of the UK's most complex, cutting-edge projects, with the chance to work across the whole boat. You will also gain exposure to an extensive range of stakeholder groups and industrial partners. We offer relocation support packages across all Submarines roles, subject to meeting eligibility criteria. Why BAE Systems? This is a place where you'll be able to make a real difference. You'll be part of an inclusive culture that values diversity, rewards integrity, and merit, and where you'll be empowered to fulfil your potential. We welcome candidates from all backgrounds and particularly from sections of the community who are currently underrepresented within our industry, including women, ethnic minorities, people with disabilities and LGBTQ+ individuals. We also want to make sure that our recruitment processes are as inclusive as possible. If you have a disability or health condition (for example dyslexia, autism, an anxiety disorder etc.) that may affect your performance in certain assessment types, please speak to your recruiter about potential reasonable adjustments. Please be aware that many roles working for BAE Systems will be subject to both security and export control restrictions. These restrictions mean that factors including your nationality, any previous nationalities you have held, and your place of birth may limit those roles you can perform for the organisation.

Analog Mixed Signal Design/Verification Engineer - Munich This is an opportunity for an experienced Analog Mixed Signal Design/Verification Engineer to be based in Munich. The company itself is a US company with a global presence, customers and offices around the world. They develop ICs for a huge range of markets and are looking for a mixed-signal design engineer to work on the verification of their mixed-mode designs. Other responsibilities include: • Working to develop mixed-signal verification plans and strategy. • Support with test/characterisation and Post-Silicon validation. • Work on the design of mixed-signal design circuits. • Help with design reviews and collaborate with cross-functional teams. An industry degree is required for the successful Analog Mixed Signal Design/Verification Engineer: Experience is required in the following: • Solid experience with Verilog-AM. • Experience running verification checks such as LVS and DRC. • Knowledge of power management applications. Desirable experience includes: • Passionate about joining a growing company. • Happy to work independently and have the drive to progress on their own.