Job Vacancy Principal Verification Engineer

I am seeking a Principal Verification Engineer to join a leading Chip and Silicon IP provider. The Principal Verification Engineer will get the chance to join some of the brightest inventors and engineers in the world to develop products that make data faster and safer. You will join a global company that makes industry-leading memory interface chips and Silicon IP to advance data centre connectivity and solve the bottleneck between memory and processing.

Responsibilities
• Create digital verification plans and work closely with system and design engineers. 
• Implement digital test-benches in SystemVerilog and UVM to apply constrained random stimulus and checks. 
• Implement Systemverilog Assertions (SVA).
• Track bugs, functional coverage, and RTL code coverage.
• Work with design and systems teams to close bugs as they arise. 
• Mentor junior designers.
For this role, at Principal level, you are required to have at least 7 years’ experience in Verification (with a PhD) or circa 10 with a BsC or MsC.

Other qualifications include:
• Significant experience with coding in System Verilog or Verilog and UVM methodology.
• Experience in Verification of DDR memory interfaces is highly desirable.  
• Significant experience with standard ASIC Verification flow/software tools.
• Experience working in Analog/Mixed-signal products is highly desirable.  
• Experience in leading and driving technical solutions across organisation.  
Being a top company, you can expect a competitive compensation package including base salary, bonus, equity, employee stock purchase plan, comprehensive medical and dental benefits, time-off program, and gym membership.

For more information and a confidential discussion please contact Rachel Mason at IC Resources.