Job position Senior Design Verification Engineer - (Security / SerDes / PCIe / USB / ethernet)
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Working for a global leader in semiconductor products for a variety of complex, high-speed products; including security and high-speed communications IP.
Senior ASIC Design Verification Engineer
€70-90k plus package (bonus, relocation, RSUs)
Visa sponsorship is available for the right candidate / applicant / engineer.
Requirements:
• Degree / Masters / PHD qualified in Electronics / Micro-electronics / Physics or similar related fields
• 8-10+ years' design verification experience of high-speed or security related IP
• Multiple project / tape-out experience of complex digital products
• UVM environments / libraries / test-benches for complex IP
• Fluent English language & communication skills
Additional / bonus / \"nice-to-have\" skills
• Work experience in Europe
• FPGA design / verification / implementation / prototyping
• emulation
• formal methods / formal verification / SVA - system verilog assertions / jasper gold / onespin
• Serdes / PCIe / USB / ethernet
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Senior Design Verification Engineer - (Security / SerDes / PCIe / USB / ethernet)
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