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Physical Design Engineer – Cork I am looking for Physical Implementation Engineers of all levels to come and join the team in Cork. This is a fantastic opportunity to join a Global Semiconductor company who are expanding their team in Cork. This is an exciting opportunity to join a large and stable company that works on all aspects of leading-edge technology. This role would best suit a Junior Engineer looking to take the next step in their career and enhance their knowledge or a Senior Engineer looking to lead a team and demonstrate their expertise. You will be using the latest tools and techniques whilst working down to advanced nm’s, 5nm’s, and below! Requirements: • Bachelors in Electronics Engineering or a related field • 2+ successful tapeouts • Good knowledge of timing and power analysis • Experience with synthesis and implementation tools – Cadence or Synopsys Being a top company, my client also offers a competitive base salary, bonus scheme, RSUs and flexible work options. If you would be interested in hearing more about this opportunity or others, then please contact Jordan Browne at IC Resources.

Senior Physical Design Engineer – Lausanne I am looking for an experienced Physical Design to come and join my client at any 1 of their 4 sites. This client is an established start-up who already have several sites across the Globe and are looking for some experienced Physical Design Engineers to come and join the team at one of these locations. They specialise on high-speed bus transfer in wireless communications and are already challenging established tech giants within the industry. Requirements: • Bachelors or Master of Engineering in Electronics or Electrical Engineering • Strong expertise across rhe full RTL To GDS implementation flow • Experience working at 28nm, 16nm, 14nm or 7nm process nodes • Experience in TCL, Shell, Python etc • Experience in tape out procedures • Expertise in Timing constraints and STA • Experience in DFT methodologies • Experience with Cadence Genus and Innovus Responsibilities would include: • Timing Constraints development, timing constraints validation, signoff Static Timing Analysis and full chip & block-level timing closure • Synthesis, floor-panning, place & route, clock tree synthesis, physical verification • Work closely with the other teams in the business This client also has sites in Germany and the UK and are happy for Engineers to work from any of these sites as well. For more information on this role or others then please contact Jordan Browne at IC Resources – [Telephone number removed] .