Job Vacancy Digital Verification Engineer - UVM

Job Title: Principal Verification Engineer 
Location: Paris or Grenoble (Full remote within France considered)

Are you a seasoned Verification Engineer with a passion for leading innovative digital verification projects? Do you excel in an environment where your expertise will be applied to advanced SoC and ASIC design? If so, we’re offering an exceptional opportunity for you to step into the role of Principal Verification Engineer and make a real impact.

About the Role As our Principal Verification Engineer, you’ll play a key role in guiding the technical verification strategy and execution for cutting-edge digital ASICs. You’ll lead a skilled team through complex verification processes, collaborating closely with digital and mixed-signal IC design specialists to deliver next-generation technology. This role offers a unique chance to shape the future of digital verification within a fast-paced, innovative environment.

Key Responsibilities • Technical Leadership: As the Principal Verification Engineer, you’ll lead the verification team in implementing a robust and efficient strategy for verifying advanced ASICs.
• Methodology Development: Work with other technical leaders to define and implement IC verification methodologies, bringing your strategic vision as a Principal Verification Engineer to the fore.
• Hands-on Execution: Oversee the development of subsystem and top-level verification plans, including writing self-checking test benches and test cases.
• Design Enhancement: Participate in the design and improvement of Verification IPs, working closely with the Analogue Mixed-Signal team for effective simulations.
• Cross-functional Collaboration: Support the Silicon Validation team in evaluating manufactured ASICs and adhere to quality assurance protocols throughout the project cycle.
About You • Educational Background: MSc or PhD in Electrical Engineering or a related field.
• Experience: Over 10 years of experience in chip-level and circuit-level verification, with specialist knowledge in SystemVerilog/UVM.
• Technical Skills: Skilled in scripting languages (TCL, Python, Makefile) with a deep understanding of the full ASIC flow, including experience in Gate-Level Simulation and/or DFT.
• Desirable Expertise: Experience with ARM/RISC V CPUs, PCIe, Ethernet, DRAM, A/D and D/A Converters, and/or RF transceivers. Familiarity with Cadence or Synopsys tools and Formal Verification is advantageous.
• Personal Qualities: A proactive and creative team player with a critical approach to problem-solving. Excellent analytical skills and fluency in English (written and spoken).
As a Principal Verification Engineer, you’ll have the opportunity to work on groundbreaking projects at the forefront of digital verification, advancing your career in a leadership role while shaping the direction of a high-performing team. Based in Paris, Caen, or Grenoble with flexible remote options, you’ll be part of a collaborative, innovative environment that values creativity, initiative, and teamwork.

If you’re ready to make a lasting impact as a Principal Verification Engineer and lead from the front in digital verification, we’d love to hear from you. Apply today or contact Lucy Edmondson at IC Resources for further details.